RISC-Ⅴ Architecture

6 Introduction to Assembly Language

6.1 Assembly Language

Assembly (also known as Assembly language, ASM): A low-level programming language where the program instructions match a particular architecture's operations.

Architecture: (also ISA: instruction set architecture) The parts of a processor design that one needs to understand for writing assembly/machine code.

Properties:

Splits a program into many small instructions that each do one single part of the process.
Each architecture will have a different set of operations that it supports (although there are similarities).
Assembly is not portable to other architectures.

Complex/Reduced Instruction Set Computing

Complex Instruction Set Computing (CISC)
- Difficult to learn and comprehend language.
- Less work for the compiler.
- Complicated hardware runs more slowly.
Reduced Instruction Set Computing (RISC)
- Simple (and smaller) instruction set makes it easier to build fast hardware.
- Let software do the complicated operations by composing simpler ones.

Code:

op dst, src1, src2

op: operation name ("operator")
dst: register getting result ("destination")
src1: first register for operation ("source 1")
src2: second register for operation ("source 2")

6.2 Registers

Assembly uses registers to store values. Registers are:

Small memories of a fixed size (in RV64, it is 64-bit wide).
Can be read or written.
Limited in number (in RV64, there are 32 registers), but very fast and low power to access.

	Registers	Memory
Speed	Fast	Slow
Size	Small e.g., 32 registers * 32 bit = 128 bytes	Big 4-32 GB
Connection	More variables than registers? Keep most frequently used in registers and move the rest to memory

Registers

Memory

Speed

Fast

Slow

Size

Small

e.g., 32 registers * 32 bit = 128 bytes

Big

4-32 GB

Connection

More variables than registers?

Keep most frequently used in registers and move the rest to memory

Some important notes about registers:

Each ISA has a predetermined number of registers, registers are built in with hardware.

Number	Name	Function
x0	zero	Always holds the value 0. Writing to it has no effect.
x1	ra	Return Address, used to store the return address when calling a subroutine or function.
x2	sp	Stack Pointer, points to the top of the stack.
x3	gp	Global Pointer, points to the global data area.
x4	tp	Thread Pointer, points to the thread-local storage.
x5 - x7	t0 - t2	Temporary/Caller-saved.
x8 - x9	s0/fp - s1	Saved registers, x8 is also used for frame pointer.
x10 - x11	a0 - a1	Function arguments/Return values
x12 - x17	a2 - a7	Function arguments
x18 - x27	s2 - s11	Saved registers/Callee-Saved
x28 - x31	t3 - t6	Temporary/Caller-saved.

Registers have no type!
In high-level languages, number of variables limited only by available memory.

6.3 RISC-Ⅴ Instructions

In high-level languages, variable types determine operation.

In assembly, operation determines type, i.e., how register contents are treated.

Operations

6.3.1 Basic Arithmetic Instructions

Examples (Assuming here that the variables a, b and c are assigned to registers s1, s2 and s3, respectively)

Integer Addition
a = b + c;
add s1, s2, s3
Integer Subtraction
a = b - c;
sub s1, s2, s3

6.3.2 Immediate Instructions

Immediates: Numerical constants.

Syntax:

opi dst, src, imm

Operation names end with "i", replace source register with an immeidate.
Immediates can up to 12 bits in size (-2048 to 2047, inclusive), and will be sign-extended to 64 bits before adding.

Example

a = b - 10;

addi s1, s2, -10

6.3.3 Data Transfer Instructions

Specialized data transfer instructions move data between registers and memory.

Store: register to memory
Load: register FROM memory

Syntax:

memop reg, off (bAbbr)

memop: operation name (lw, sw, ...)
reg: Register for operation source or destination.
bAbbr: Register with pointer to memory ("base address")
off: Address offset (immediate) in bytes ("offset")

Example

Load Doubleword
a = array[3];
ld s1, 24(s2)
Store Doubleword
array[10] = 3;
sd s1, 80(s2)

6.3.4 Control Flow Instructions

Labels in RISC-Ⅴ: Defined by a text and followed by a colon (e.g., main:) and refers to the instructions that follows; generate control flow by jumping to labels.

Examples

Jump
Branch If Equal
if (i == j) { a = b; /* then */ } else { a = -b; /* else */ }
beq s0, s1, then else: sub s2, x0, s3 j end then: add s2, s3, x0 end:
Branch If Not Equal
if (i != j) { a = b; /* then */ } else { a = -b; /* else */ }
bne s0, s1, then else: sub s2, x0, s3 j end then: add s2, s3, x0 end:
Branch Less Than
if (i < j) { a = b; /* then */ } else { a = -b; /* else */ }
blt s0, s1, then else: sub s2, x0, s3 j end then: add s2, s3, x0 end:
Branch Greater Than or Equal (bge)
Branch Less Than Unsigned (bltu, treat registers as unsigned integers)
Branch Greater Than or Equal Unsigned (bgeu)

Program Counter:

Program Counter (PC): A special register that contains the current address of the code that is being executed, and not accessible as a part of 32 registers.
Branches and Jumps change the flow of execution by modifying the PC.
Instructions are stored as data in memory (code section) and have addresses! Labels get converted to instruction addresses.

6.3.5 Shifting Instructions

Instructions Table

Logical Operations	C Operators	RISC-V Operators
Bit-by-bit AND	&	`and`
Bit-by-bit OR	\|	`or`
Bit-by-bit XOR	^	`xor`
Shift Left Logical	<<	`sll`
Shift Left Logical Imm	<<	`sll1`
Shift Right Logical	>>	`srl`
Shift Right Logical Imm	>>	`srli`
Shift Right Arithmetic	>>	`sra`
Shift Right Arithmetic Imm	>>	`srai`

6.4 C, Assembly & Machine Code

Compile with the following code (debugging-friendly):

gcc –Og p1.c -o p

Use the following command to generate the assembly code:

gcc –Og –S p1.c

Use the following command to disassembly the machine code:

objdump –d p1

Last modified: 08 December 2024